AMD could introduce Instinct MI200 and Milan-X on November 8

Lisa Su, CEO of AMD has confirmed through Twitter that on November 8 a very important event will be held for the Sunnyvale company, in which the executive will be in charge of presenting the most relevant news for the future, in the short and medium term, of AMD.

Although he has not gone into specific details we know, from previous leaks and from what is deduced from the image he has shared, that this new event will be centered around two major keys, the Instinct MI200 graphics accelerators, which will use the CDNA 2 architecture, and EPYC Milan-X, a new generation of server processors that will maintain the MCM design and Zen 3 architecture as a base, but that will come with 3D stacked cache.

The Instinct MI200 accelerators could mark an important evolution in the sector because, according to the most recent information, they will be the first to use a multi-chip module design, which means that their GPUs will no longer have a monolithic core design, but will instead combine multiple chips to create a “super GPU”. The idea is, in short, the same that we saw with Zen and its subsequent evolutions, combining small chips with a relatively low number of cores to create more powerful configurations with a greater number of cores.

As for the EPYC Milan-X processors, the most important novelty we have already commented on, would be the inclusion of L3 cache stacked in 3D, that is, vertically. The approach would be very similar to what we have seen, for example, with 3D NAND Flash memory, or with HBM memory, to give two well-known examples.

Each processor within the Milan-X series could have double, or perhaps even triple, the L3 cache memory of previous generations. This memory serves as a fulcrum for the CPU to store instructions and data that it needs to access on a regular basis. When the cache fills up, you have to move the new data and instructions to RAM.. Since accesses to RAM are slower than to cache, there is a loss of performance.

Well, having a larger third-level cache, it would be possible to store more instructions and data in it, and reduce the amount of requests required to RAM, which would result in a considerable performance improvement. I can’t specify yet, since we don’t have specific data, but I would dare to think that that extra L3 cache could boost the CPI between 10% and 20%.

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