Although we know little about Zen 5 and the Ryzen, Threadripper and EPYC processors that AMD will launch under this architecture this does not mean that those of Lisa Su are not working on it, with Zen 4 already in the final phases of the design it is normal that the fifth generation architecture is also quite advanced.
AMD EPYC Zen 5 will use the SP5 socket
The Socket SP5 It will be used for the first time by the AMD EPYC based on Zen 4, with Genoa being the first model to launch with 96 cores and in second place Bergamo with 128 cores. Well, the AMD EPYC Turin will also use the same socket.
According to rumors this processor will have a 600 W maximum consumption and therefore will make use of the Socket SP5 type E that allows up to 700 W of consumption. From recently leaked details we know that it is a CPU socket of the type LGA with 6096 pins. Apparently the new socket can reach its maximum consumption during 1 millisecond of time and 440 W during a period of 10 ms.
Another detail that has been leaked about the new socket and specifically the chipset with which it will be compatible is that the AMD server CPUs based on Zen 4 will use DDR5-5200 memory interfaces, but the AMD EPYC will increase the speed to DDR5-6400. It is also rumored that we could see the implementation of interfaces for the first time PCI Express 6.0.
New details of the Zen 5 cores
If the socket of the AMD EPYC Turin It is the same as its predecessors, as well as the EPYC processors based on Zen 3, they use the same as Zen 2, so at first glance the Zen 4 and Zen 5 processors should look the same in terms of size and the amount of CCD chiplets in them.
We have more than confirmed that each CCD chiplet of the Zen 4 architecture will use an 8-core configuration as in the current Zen 3. So we are talking about designs of 12 CCD chiplets for Genoa and its 96 cores and 16 for Bergamo and its figure of 128 Cores.
ZEN5 EPYC should also have two configurations.
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Of course, this conflicts with the information that the insiders have just given, where they talk about designs with twice the number of cores, since the AMD EPYC Turin based on Zen 5 will have configurations with a greater number of cores than those of Fourth generation: 192 with 384 threads and 256 with 512 threads.
According to rumors, the Zen 5 CCD Chiplets will be manufactured under TSMC’s 3 nm node, which has a density 1.6 times its 5 nm node, so by eliminating redundancies it would be possible to place twice as many cores, but we We can forget about the interface to communicate the 16 cores, which would be extremely complex, so we should not rule out an intermediate node such as N4 or N4P.
Another detail that has been revealed is that Zen 5 will make use of the V-Cache in all its designs, something that by the way we do not know if Zen 4 will implement it as standard as a measure to increase its performance. In any case, it is proven that increasing the amount of L3 cache increases the IPC considerably. AMD may completely separate the L3 cache from the rest on the Zen 5 cores to reduce its size.
Heterogeneous cores in Zen 5?
What is the other possibility? We know that AMD has published a patent for the use of heterogeneous cores and that it could see the light at least in Zen 5. So AMD could adopt the same strategy that Intel has just adopted and therefore half of the cores will be smaller size. The difference with Intel’s approach? All cores would support multithreading and not just high-performance ones, but this is not something we can confirm.
One thing that rules out this approach is that in the case of the AMD EPYC Turin we are talking about a processor for servers where the use of highly energy efficient cores does not usually occur, in any case AMD’s approach to a hybrid configuration does not it has to be totally the same as Intel.