Zen 4 is the new generation architecture that AMD will use in its next generation of high-performance processors, both for the general consumer market, where it will debut under the Ryzen 7000 nomenclatureas well as for the professional market, where it will give life to processors EPYC Genoa.
The information that we had been seeing so far pointed to important developments. Two of the most relevant are the jump to the TSMC 5nm nodewhich will be a clear evolution from the 7nm node that AMD has used with Zen 2 and Zen 3, and also a CPI increase which could allow it to reclaim the crown of single-thread performance.
Thanks to a new leak, we have also been able to confirm an important detail about Zen 4, and that is that AMD is going to double the amount of L2 cache memory per core, which It goes from the current 512 KB to a total of 1 MB (1,024 KB). It’s important to note that we’re talking about a per-core count, which means a 64-core, 128-thread Zen 3 processor only adds 32MB of L2 cache, while a Zen 4-based version of it would have 64MB of L2 cache. L2 cache.
Increasing the L2 cache should result in a significant performance increase, although curiously in this leak we have not seen an increase in L3 cache. That said, this is curious because AMD has used vertically stacked L3 cache recently, both in its new EPYC Milan-X series and in the Ryzen 7 5800X3D.
This means that EPYC Genoa, AMD’s next generation of Zen 4-based high-performance professional processors, will retain the 32MB L3 cache configuration per chiplet, but will have 1MB cache per core. Since the most powerful configuration will have 96 cores and 192 threads, this would leave us with a total count of 96 MB of L2 cache and 384 MB of L3 cache. A simple sum gives a total of 480 MB of total cache (not counting L1).
Coming later this year, AMD’s EPYC Genoa processors will support 12-channel DDR5 memory configurations and have a maximum TDP of 400 watts. Shortly after, the EPYC Bergamo will arrive, based on Zen 4c and configured with up to 128 cores and 256 threads. They will also use DDR5 memory configured in up to 12 channels. Both will be grouped within the 7004 series, indicating that they will succeed the current 7003.