The history of CPUs for PC can be divided into two halves, on the one hand the era of single-core processors and on the other hand the multicore era in which we find ourselves. The phenomenon that caused the paradigm shift? The end of Dennard’s climb. Now after more than 15 years with multi-core processors, the problem is when it comes to scaling the number of them beyond the current figures.
With Intel betting on heterogeneous cores of disparate size, consumption and complexity within the same processor from Alder Lake and AMD with Zen 5, it is clear that the number of cores will increase. In any case, and in any case, the increase in the number of processors implies an increasing complexity in their infrastructure.
Complexity of infrastructure and energy consumption
To understand the reason for the purchase of Xilinx by AMD, we must bear in mind that the objective is none other than the use of SmartNICs or intelligent network controllers to control the communication infrastructure of the different cores. Although first of all we have to understand what the problem is.
If I, for example, have 4 cores, then I will only need 12 links to intercommunicate the different cores between them, but if I have 8 cores, things get more complicated and I end up needing a total of 56 links, so imagine with one greater number of nuclei.
These intercoms between processors not only require a more complex infrastructure, but these cables consume power. The solution? Use other types of communication interfaces such as rings, which make use of less cabling and connections in exchange for higher send latency, which is what AMD has done in Zen 3.
Rumors suggest that Zen 4 will have the same number of cores per CCD, which are 8, where in any case its design is prior to the purchase of Xilinx and rather It will be in Zen 5 where we will see the use of this company’s technology in AMD CPUs with the aim of increasing the number of possible cores in a processor.
This is how Xilinx technology will be used in future CPUs
There is no doubt that the infrastructure of AMD’s Zen 5 processors will harness the full potential of Xilinx technology. In the center of the processor there will be a SmartNIC that will be in charge of receiving all the requests between the different cores for communication, which is much more efficient than using certain communication infrastructures. Let’s not forget that although some of them save on the number of connections they add latency and are counterproductive in performance from a certain number of cores.
After all, it is still the same as Intel has done with its IPU, which will be used for the first time in Xeon Sapphire Rapids, and after all it is the path that the entire industry is following to move to the era of the dozens of nuclei.
So AMD will replace the now classic “Scalable Data Fabric” like Northbridge of its future Zen by a Xilinx intelligent network controller in the central part of its processors. Since the SDF has been used in both the CPU and GPU design, the conclusion is that the change will not only occur in future processors, but also in graphics cards where obviously the number of cores will also increase and we will see multi-chip designs.