Ceremorphic presents a new architecture designed for AI and HPC

Ceremorphic is a startup that was founded in april 2020 and that, despite its short existence, it has been able to carry out a very ambitious project, thanks to the experience that its members have in the world of semiconductors, and also thanks to its intellectual property portfolio, which is made up of more than 100 patents.

The company has announced the development of a new architecture with which it will be able to respond to the growing challenges of sectors such as AI, high performance computingadvanced computing in the world of the smart car, scientific research, and the workload that will go into developing, and creating, the metaverse.

This new architecture uses the TSMC’s 5nm node, and it was developed from scratch with the aim of responding to all the challenges posed by the sectors that I have mentioned in the previous paragraph, betting on key values ​​such as reliability, safety and efficiency. Venkat Mattela, founder and CEO of Ceremorphic, commented:

“Having developed many innovations in multi-threaded processing, algorithm-driven VLSI, reliable performance circuitry, low-power interface circuitry, quantum resilient security microarchitecture, and new device architectures beyond CMOS, Ceremorphic is well on its way.” to achieve our goals. The challenges this market faces with ‘reliable performance computing’ cannot be solved with existing architectures, but instead requires an entirely new architecture built specifically for reliability, security, power efficiency and scalability.”

Ceremorphic’s answer has been a Hierarchical Learning Processor (HLP) that has the following specifications:

  • Custom machine learning processor (MLP) running at a frequency of 2 GHz.
  • Custom FPU (Floating Point Unit) that also operates at a frequency of 2 GHz.
  • Proprietary multi-threaded macroarchitecture, ThreadArch-based RISC-V processor for proxy processing at 1 GHz frequency.
  • Custom video engines for “Metaverse Processing” at 1 GHz, along with an ARM M55 v1 core.
  • Custom PCIe 6. 0 / CXL 3.0 x16 connectivity interface.
  • Open AI Framework software support with optimized compiler and application libraries.
  • Error rate: (100,000) -1.

The architecture presented by Ceremorphic has been designed to offer a high level of scalability, and to fit seamlessly into multiple sectors, as we have seen at the beginning of this article. We can find more information on their website.

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