The arrival of new technologies always aims to meet two important requirements. The first one is to increase performance over previous systems and the second is to make a specific task easier and more accessible. Those of the first case are normal in PC, since from time to time more powerful peripherals and components come out, those of the second type are rarer and appear in longer periods of time. A historical example is the USB port, which replaced several peripheral interfaces at the same time and progressively, simplifying and making the use of the PC more accessible.
Well, the arrival of DDR5 memory is going to be an improvement in the performance of our PCs. Especially due to the fact that its improvements are remarkable enough to get a superior performance compared to DDR4 under the same processor. One of the keys being the ability to support two memory channels at the same time. However in an era where CPUs are fully multi-core, having memory capable of supporting multiple memory channels at the same time becomes a necessity.
This would lead us to the development of a DDR6 memory in a very tight time, where the designs of all kinds of components such as CPUs, chipsets, motherboards would have to return to the design table for the adoption of a new form of memory after DDR5 . However, the CXL interface offers the solution and completely changes the paradigm after several decades.
The CXL interface will be used to expand the RAM
So far we have been able to see how the memory interface of a CPU and that of peripherals and components is different, especially because the PCi Express is a port that by itself does not offer coherence with memory. So it requires other internal mechanisms in the system to achieve it. In a simplified way, the CXL is a superset of PCI Express 5.0, but with the difference that it has the necessary mechanisms for consistency.
But the most interesting part of the CXL is its so-called memory sub-protocol, which it’s allows you to create additional memory interfaces and therefore use the PCIe 5.0 interfaces with CXL support for:
- Expand the total system bandwidth and / or its capacity beyond what the processor could by using only its DDR5 memory interfaces. This means a significant performance increase as there is less contention and the ability to meet the data demand of a greater number of cores. when expanding memory channels.
- It allows the use of different types of memory in a system, which would be fully communicated without problems. In addition to allowing to increase the amount of RAM that due to chipset limitations it can support.
This opens up a series of possibilities that will make us say goodbye to the classic DDR memory interfaces in CPUs.
A change that has already started
We already saw this a few months ago with the launch of a PCI Express card with RAM memory by Samsung, which uses a CXL interface to precisely do what we are talking about in this post. However, despite the fact that for the moment this expansion is going to go to the server CPU market, we cannot forget that The CXL interface opens the possibility of using the PCIe lines that are not used to expand the capacities of the RAM memory of our system. We may even see future DIMMs that do not interface with the classic DDR5 memory interface, but with a CXL interface embedded in the processor.
So in conclusion, the CXL like the USB can become an interface that replaces the memory interfaces of the future. Imagine for a moment an AMD, Intel or NVIDIA CPU that does not have a specific memory interface, but a CXL that allows you to install several different memory configurations. This is important, since at this point it is necessary to integrate each type of memory interface into the perimeter of the chip, which increases its size.
So, at present if a CPU or an APU supports DDR4 and LPDDR4 memory, as their specifications are not the same then you need to have both interfaces on one chip or create two different models of the same processor. All this will be avoided thanks to the use of the CXL interface to replace the RAM memory in future processors.