Final specifications of HBM3 memory: Up to 64 GB

JEDEC has published the final specifications of the HBM3 standard, a revision of the well-known format of 3D stacked high performance memory which represents an important advance compared to previous generations, and which will be used in components that require high bandwidth, such as the next generation graphics accelerators from NVIDIA and AMD.

HBM3 memory maintains the base of the previous generation, that is, stacking of chips vertically. This makes it possible to reduce the space it occupies on the PCB, and at the same time plays an important role in the maximum density that we can achieve per chip.

This new standard is part of a 4 GB base configurationand will peak in a maximum of 64GB. The number of independent channels has also been doubled compared to the HBM2 memory, which means that it goes from 8 to 16, although thanks to the presence of two pseudo channels, real support is triggered at 32 (virtual) channels.

The maximum stack of chips that it will allow in its first review will be 12 heights, but in the future it will jump to 16 heights. The chips are interconnected using the classic “Through Silicon Via” system, or TSV for its acronym in English. This new standard also marks a huge leap in terms of speed, as it is capable of reaching a bandwidth of 819 GB/s per chip.

As expected, this memory comes with error correction technology (ECC)which makes it a completely reliable option for carrying out very complex tasks that require total precision, such as scientific simulations, for example, in which the slightest error in the data can generate a discrepancy so serious that it ends up ruining large duty cycles.

On the other hand, this memory has also introduced improvements in terms of efficiencysince it uses a low swing signal on the host interface, 0.4 volts, and has a voltage of 1.1 volts.

with this memory it will be possible to break down some barriers that exist today in the professional sector, something that was pointed out by Barry Wagner, director of technical marketing at NVIDIA and chairman of the JEDEC HBM subcommittee, commenting on the following:

“With its performance and reliability enhancements, HBM3 memory will make new applications possible that require high bandwidth and high memory capacity.

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