With the leak of NVIDIA data in the theft of data for its servers, not only has its roadmap in terms of graphics architectures come to light, but also the configuration of the RTX 40 GPUs based on the Ada Lovelace architecture that NVIDIA will release sometime in 2022. How do they compare to the current generation?
Gossips have long claimed that the Ada Lovelace architecture of the RTX 40 was initially known as Ampere 2.0 and it would be a very similar move to what NVIDIA did with the GTX 900 and GTX 1000, where they transferred the 28nm Maxwell architecture Bulk at 16nm FinFET, they added some minor improvements and a larger number of cores in the process. In the case at hand, it would be the transfer of the 8nm node from Samsung to the 5nm node from TSMC.
NVIDIA RTX 40 GPU Configuration
It turns out that information has been leaked about the number of SMs, which is what NVIDIA calls its shader units or actual GPU cores, that have the different configurations of the Ada Lovelace architecture. Let’s not forget that NVIDIA also calls the FP32 units inside the SMs CUDA cores.
The information in summary is as follows:
- The AD102 chip has a total of 144 SM (18,432 CUDA cores)which is a significant jump from the 84 SM of the RTX 3090 Ti.
- In second place we have AD103 with 84 SM (10,752 CUDA cores)just the same figure as the current GA102 of the RTX 30. From what we deduce that it is a conversion of said chip to 5nm from TSMC.
- In the case of the AD104 we have a configuration of 60 SM (7,680 CUDA cores)12 more than the current GA104.
- AD106 has a setting of 36 SM (4,608 CUDA cores). The current GA106 has a setting of 30.
- The most modest chip would be the AD107 with 24 SM (307 CUDA cores). So in the lower part of the table there are also improvements with 4 more SMs.
How do we interpret the data?
Let’s not forget that NVIDIA GPUs are a kind of Matroska in which 2 SMs are part of a TPC.
And up to 6 TPCs are part of what we call a GPC.
If the architects who work for Jensen Huang have kept the structures of their previous two generations in the RTX 40, which we don’t know, then the configuration of the RTX 40 regarding the number of GPCs that we will have would be the following in ascending order of power:
- AD107 or RTX 4050: 2 GPCs and a potential 128-bit GDDR6 bus.
- AD106 or RTX 4060: 3 GPCs and a potential 192-bit GDDR6 bus.
- AD104 or RTX 4070: 5 GPCs and a potential 256-bit GDDR6 bus.
- AD103 or RTX 4080: 7 GPC and a potential bus of 320 bits or 384 bits GDDR6 at high speed.
- AD102 or RTX 4090: 12 GPC and a potential bus of 384 bits or 512 bits of GDDR6 at very high speed.
Goodbye to GDDR6X in the next generation of NVIDIA?
Not long ago, RAM manufacturers introduced their GDDR6 at 20 and 24 Gbps, which puts them at the same bandwidth as GDDR6X. Of course, with a considerable increase in consumption in the process due to the increase in voltage to reach 20 Gbps and 24 Gbps transfers, but gaining the ability to have 2 GB capacity chips.
We do not know if NVIDIA will use the 600 W connector, but we can be sure that it will use the 450 W one, since it has already used it in its RTX 3090 Ti. The configuration of 12 GPC with 144 SM inside requires enormous bandwidth, despite the fact that a 384-bit configuration is the one with the most numbers, from here we anticipate that you do not rule out the increase in consumption margins due to the new connector a configuration for the most powerful 512-bit RTX 40.
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