Hell freezes over, Intel manufacturing its CPUs at TSMC?

What would happen if we told you that Intel could manufacture one of its CPUs outside of its factories? Well, this is what is being said about one of its future CPUs, and it is that rumors have appeared that they will use TSMC’s N3 node to manufacture Arrow Lake-P. To what extent could this be true or just hearsay?

Intel’s plan for the coming years to release a new generation of its CPUs on an annual basis forces them to have their designs already quite advanced years in advance of their launch. This is the case of Arrow Lake, the so-called fifteenth generation of the Intel Core, of which some specifications have been leaked despite the fact that the Intel Core 13 has not yet been released.

In any case, we should not be surprised since Intel announced months ago that the Compute Tile that includes the cores of the Intel Core 14 was already finished and we are talking about a CPU that we will not see until well into 2023. What’s more, the idea of ​​adopting a design by chiplets, or tiles for Intel. Something that allows the entire industry in general to be able to accelerate the deployment of its new processors.

Intel Arrow Lake manufactured at TSMC N3?

Arrow Lake TSMC N3

In the last hours, rumors have appeared about the specifications of a processor for laptops that would correspond to the Intel Core 15 for laptops or Arrow Lake-P. They tell us about 6 P-cores and 8 E-cores and one 320 EU tGPU, it should be noted that Intel intends to progressively improve the performance of these cores in each generation. Although the most surprising of all is not a configuration that falls within what is expected, but the manufacturing node that according to rumors will be used by Intel.

It can be understood that Intel decides to use TSMC to manufacture the GPU in order to decongest its factories and due to the fact that it will also manufacture its ARCs at TSMC. What do the rumors say? Well, what in Intel will make use of TSMC’s N3 node at Arrow Lake-P also for the manufacture of the Compute Tile. Which would mean the first CPU that Intel would not manufacture itself and would be made by a third party.

Intel road mapThis conflicts with the information given by Intel itself a few days ago.where they commented that while Meteor Lake will make use of their Compute Tile for their Intel 4 node, so Arrow Lake will use the Intel 20A process for the first time. Another thing that makes us skeptical about these specifications, unless it is a very low power unit, is the very low number of E-Cores, especially when we know that they are going to double in Raptor Lake, going from 8 in current CPUs to 16.

As for the Tile GPU in Arrow Lake, a 320 EU configuration shouldn’t surprise us considering the use of a crafting node that’s a generation higher. Especially considering that we are expecting a major update to counter RDNA 2 iGPUs on AMD.

The information would be out of date

In any case, the information in the rumor would be outdated at the moment, since according to whoever leaked it, its information comes from an internal document from Intel itself. So in theory this would show that Intel would have considered at one point in time to use TSMC’s N3 node for Arrow Lake to manufacture the tile corresponding to the CPU.

In any case, these rumors conflict with the news that we mentioned yesterday where we told you about the rumor that AMD would be having problems with TSMC’s N3 node and would have decided to manufacture at Intel. Which is something just as surprising as the topic we are dealing with in this news. There is still a long way to go before the deployment of 3nm in the PC, especially when CPUs, GPUs and other 5nm processors have not even been released on the market. Therefore, only time will tell what these movements are due to and if there is a political or strategic reason behind it instead of a technical reason.

The post Hell Freezes Over, Intel Making Its CPUs at TSMC? appeared first on HardZone.

Related Articles

Leave a Reply

Your email address will not be published.