IBM and Samsung design transistor stacking system that can lead to more efficient chips

IBM Y Samsung, taking advantage of the framework of the conference IEDM which is being held in San Francisco (United States), have unveiled a new design that allows transistors to be placed vertically on a chip. Today, according to Engadget, with today’s processors and SoCs, transistors are placed horizontally on the surface of the device, and when they work, electrical current flows through them from side to side. Through this new system, the new transistors, which have been called Vertical Transport Field Effect Transistors, or VTFETs, are placed perpendicular to each other, and the current flows vertically.

According to both companies, this design has two advantages. On the one hand, it allows removing many performance limitations to extend Moore’s Law beyond IBM’s current nanosheets technology. In addition, with this design they consume less energy, because the current flow is greater.

Both IBM and Samsung estimate that VFTET transistors will lead to processors that are either twice as fast or consume less than 85% less power than chips designed with FinFET transistors. The two companies assure that with them it may be possible that in the future they will be able to manufacture mobile phones with an autonomy of one week. Apart from this, they could support specific tasks that require a lot of energy consumption, such as mining cryptocurrencies, in a more energy efficient way, which would reduce the impact on the environment.

But for now, neither IBM nor Samsung have specified dates to start commercializing the VFTET design. In addition, they are not the only technology that is trying to overcome the barrier of the nanometer. Last July, Intel said they intended to have an angstrom-scale chip design ready by 2024, and that they plan to do so with their new Intel 20A node and RibbonFET transistors.

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