The hardware of our PCs only does one thing, transmit electrical signals at different voltages between its components. Depending on the voltage used, the information that is transmitted has one meaning or another. As new manufacturing nodes have been created, new phenomena have occurred, but the one that has worsened the most has been the RC Delay.
What is the RC Delay?
RC Delay can be translated as the delay of the electrical signal produced by the combination of the resistance and the capacitance of that part of the circuit. When we talk about resistance we are talking about the difficulty that electrons have to pass through that particular part of the circuit. The capacitance, on the other hand, is the capacity that this part of the circuit has to store the electrical charge.
The RC Delay has become in recent years one of the biggest problems for designers of new chips under new manufacturing nodes. The reason? We normally have the concept that chips are made up of logic gates, which are made up of transistors. The reality is that these logic gates are interconnected with each other through a micro-wiring that runs through the circuit and through which the different electrical signals are sent.
So that the signal that separates one logic gate from another is transmitted without variations in the electrical signal that can lead to a variation of the unwanted information, what is done is to place layers of dielectric material between the cables through which the signal is transmitted. The problem is that as the density per area becomes larger with the new manufacturing nodes, then at the same time the distance between the micro-wiring decreases and thus the risk that the signal is distorted increases.
Signals and circuits
We tend to understand that any digital integrated circuit works by making use of ones and zeros, which is a simplification of the concept. In reality we are talking about transmitting information through the internal micro-wiring of the chip under two different voltages where it varies from one to the other continuously.
What is important in a circuit is not only that the signal is transmitted correctly, but that it is transmitted in the appropriate period. The RC Delay also assumes the speed at which the electrons circulate through the electrical circuit and therefore influences the final clock speed of the processor.
The problem in the last nodes? Although the transistors have scaled within the expected, the wiring has not done so to the same degree and they are comparatively larger with respect to the previous nodes and therefore the clock speed has not scaled as expected. In other words, it is the interconnection between the different logic components of a processor and its internal memories that led to the end of the MHz race.
The Rent rule and its relationship with the RC Delay
Rent’s rule is related to the organization of computational logic within a chip and specifically to the wiring that interconnects the different logic modules that are part of a processor when it is on the design table. What is the Rent rule for? Well, to know how many interconnections a microprocessor is going to have.
The formula for the Rent rule is as follows:
T = AKp
Where T is the number of terminals and therefore of micro cables in the entire chip, A is the average number of micro cables within each logic block and K is the average number of logic gates in each block within the chip. What does it have to do with the RC Delay? Well, because the Rent rule allows system architects not only to know the wiring and location of their designs, but also the length of the micro-wiring and therefore the RC Delay.
We cannot forget also that the distance of the cabling is also related to energy consumption and the longer a cable is, the greater the consumption in data transfer, so architects have to know how to balance between the expected clock speed and the chip power consumption.
Not all hope is lost
The RC Delay despite being an existing problem is not something that is being ignored by the creators of new microprocessors and memories. There are advances in recent years that have to do with the objective of alleviating the growing problem of the RC Delay with the new manufacturing nodes, in particular two types of advances are being used in parallel:
The first of these is the search for new dielectric materials that allow more efficient isolation of the electrical signal that is distributed through terminal to terminal. So a good part of the research and development for the new manufacturing nodes to create new CPUs, GPUs and memory is not only based on reducing the size of the transistors, but on solving the problems that arise with the new nodes.
The second is in the use of vertical structures for the intercommunication of the elements, with which we do not increase the number of terminals, but if the distance between them and therefore we end up reducing the possibilities that the signal from one microcable affects another by the distance between these. The only problem with this approach? At the moment we have seen implemented on a large scale what are vertical interconnections of memory over memory and even logic over memory, but the future points to the fact that we are going to see logic over logic in order to scale the clock speed of the different processors.