Intel disappoints with their new CPUs, more TDP, and DDR5 worse than DDR4?

As you may already know, the new generation of Intel processors represents a turning point in the industry, since it will be the first platform with heterogeneous cores for the desktop, but also because it will be the first to use the new generation of DDR5 RAM, two reasons where all eyes are on performance numbers.

The Alder Lake P and M Power Limit for Laptops

The new leaked data expands the information on the power limit with the fourth level, which is precisely the most interesting because it is the one that describes the maximum power. The patch lists the power for four different Intel Alder Lake CPU configurations:

  • Alder Lake-P (2 + 8 + 2)
  • Alder Lake-P (4 + 8 + 2)
  • Alder Lake-P (6 + 8 + 2)
  • Alder Lake-M (2 + 8 + 2)

Each of these numbers describes respectively the high-performance (large) cores, the high-efficiency (small) cores, and the graphics cores, which in this case are already known to have the Intel GT2 iGPU of 96 execution units.


The data has been collected and compared to the Tiger Lake series, which is supposed to replace the 12th Generation Intel Core. However, it is worth remembering that the Alder Lake notebook series will be divided into three segments (M, P and S) which in turn divide into six power groups. The data that appeared on Corebook appears to include an Alder Lake-M U9 (9W) and Alder Lake-P U15 (15W); According to the leaks, they are supposed to represent ultra-slim designs for general-purpose laptops, exactly what Chromebooks are supposed to be, and therefore are so low peak power.

The Power Limit 4 o PL4 rates the pack power limit that the power adapter and battery should not exceed for more than 10 ms. This is the highest power the processor package can achieve, and should not be confused with limits PL1 and PL2 used the vast majority of the time. In general, we are seeing PL1 and PL2 power levels similar to the Tiger Lake-U series, but with slightly higher peak values.

Given that the Tiger Lake-U series will be replaced by these next generation series, it is difficult to make a direct comparison although it seems clear that the M series should only be offered for ultra-thin notebook designs, possibly even with passive cooling, while the series Q yes it will require active cooling.

RAM performance: DDR5 vs DDR4

TeamGroup DDR5

Rumor has it that the next generation of processors 12th Generation Alder Lake Intel will support both DDR4 and DDR5 RAM, and yet a recent leak has shown that performance could be affected by this. An Alder Lake CPU sample reportedly features 16 cores and 24 threads, something we’ve seen before. Taking into account that this new generation is heterogeneous and that it has “big” and “small” cores but only the big ones have Hyperthreading, the chip should have 8 cores Golden cove and 8 Gracemont.

Today’s news marks the second appearance of a chip of this generation, also 16-core and also in UserBenchmark, but in this case using DDR4 memory. This sample apparently has a base frequency of just 1.8 GHz and a Boost frequency of 3.65 GHz, so it seems clear that this is an engineering sample again. This is relevant because obviously the faster chip should have better memory performance, but in any case we must take these figures for what they are.

Kingston DDR4-3200 2x8GB Micron DDR5-4800 2x8GB
Multi Core Read 41.5 33.6
Multi Core Write 37.0 30.8
Multi Core Mixed 28.8 30.2
Single Core Read 15.4 15.4
Single Core Write 30.2 31.4
Single Core Mixed 22.1 22.4
Latency 136 86.7

The DDR5 platform consists of two memory modules 4,800 MHz DDR5 Micron 8GB each, while the DDR4 platform has used a pair of Kingston’s 3,200MHz HyperX Fury modules, also 8GB per module. The thing is, DDR4 memory has outperformed DDR5 in these tests by practically 24% in read tests and 20% in write tests, so it’s obvious that something is wrong with these results where DDR5 it only outperforms current DDR4 in the latency test.

We repeat that “something is wrong” here and it is because the tests have been carried out with engineering sample CPUs that do not even remotely have the actual operating values ​​that commercial products will have, but in any case there are the preliminary results.

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