The codename of the future Intel Sapphire Rapids with HBM memory already has an official name by the company now led by Pat Gelsinger, specifically the model name is Intel Sapphire Rapids-SP and differs from the standard Intel Sapphire Rapids by the use of HBM2e memory. Specific Intel has opted for the use of 4 stacks of 8 chips each, which on the one hand means being able to reach the largest possible memory capacity and on the other hand they are much more expensive than traditional batteries of 4 chips each.
There are no differences in bandwidth compared to stacks of 4 memory chips and 8 chips, but the differences are reduced to the storage capacity and nothing else. It is not a special type of HBM2E memory either, since the batteries with 8 vertical chips integrated in a single memory chip are within the JEDEC standard for this type of memory. Which we remember that we have seen used in recent years in GPUs for high performance computing such as NVIDIA Tesla or AMD Instinct.
In any case, the implementation of HBM is not a novelty in the market for server CPUs, there are already cases of processors with ISA ARM that use HBM memory instead of DDR. Especially in those who work with large volumes of data, where HBM memory becomes the best possible type of memory for these processors.
This is the Intel Sapphire Rapids-SP with HBM memory
HBM memory, unlike the classic DDR, does not communicate through a classic parallel interface, but rather require the use of an interposer on which is placed both the processor that is going to communicate with the memory itself, as well as the HBM memory stacks. These types of configurations are called 2.5DIC and they are a type of packaging and therefore to build a chip different from the traditional way.
To build Sapphire Rapids, Intel will use its EMIB technology, with which you can place the 4 tiles or chiplets that make up the Sapphire Rapids SP as well as the HBM memory stacks. Which will make use of DDR5 memory as the main RAM, but it also allows you to build the version with HBM memory. While the standard version has 10 EMIB interconnects and is mounted on a huge 4446mm square packaging for the standard version, the version with HBM increases the number of EMIB interconnects from 10 to 14 and the size of its packaging to 5700 square mm. What a different socket type could mean for the Sapphire Rapids SP
The inclusion of HBM memory in the Sapphire Rapids-SP has to do with the inclusion of tensor units in the processor. Specifically, Intel’s new AMX units, which are key for Machine Learning, one of the branches of artificial intelligence. These are units that work with large amounts of data and whose performance depends on the bandwidth of the external memory. So Intel Sapphire Rapids SP with HBM memory are targeting the artificial intelligence market.
