Since 22 nm it has already rained a lot, but that is the crucial moment where Intel began to implement FinFET transistors that will soon see their end, but this is precisely the starting point to mark the inflection and what is to come. FinFET as transistor technology improved the so-called “Area Gate” with a 3D structure very advanced for its time and as such the scaling of the total area per transistor was improved.
This put in check the current measurements at that time and marked a different nomenclature and an objective jump where Intel decided to change the name of its nodes and hence the 22 nm for 300 mm wafers was born.
What happened next? Many know the story: TSMC came, saw and won, at least momentarily, which by integrating a more advanced lithographic process implies that they can somehow do better marketing than Intel, at least so far.
The problem that we have dealt with from time to time is that there is no unification of criteria for naming transistors as such, because each company takes advantage of the improvements they implement and chooses a way to determine the advantage.
Comparatively, an Intel Pitch Gate with the same nomenclative number has nothing to do with TSMC or Samsung and vice versa, that is, the 10 nm of some does not technically correspond to those of the competition, we choose the manufacturer we choose. From a marketing point of view, the smaller number implies a smaller size of the transistor and this would result in a better area, but this is not true in the vast majority of cases.
New names: Intel 7, Intel 4, Intel 3 and Intel 20A
Intel’s current 10nm is a bit more advanced than TSMC’s 7nm and one step ahead of Samsung’s 8nm and the same will happen in just over a year with its 7nm versus 5nm and 3nm of its rivals (minus Samsung with GAA, if it arrives on time).
Therefore, the blue giant had to put some order and organize its technical characteristics with the fixed nomenclatures, because they were not working in the general public. Therefore, and respecting the current 10 nm to which the “SuperFin” tag has been added, the problem is that this initially created controversy because it seemed that the 10 nm + would have that name and it is not really the case.
This is due to the alignment that we have mentioned above and that leaves the way paved for the future with 4 key names that we will explain below with more data in hand: Intel 7, Intel 4, Intel 3 and Intel 20A, where those of Santa Clara have completely dispensed with the tagline “nm”.
The evolution of 10 nm called first 10 nm + and then 10 nm SuperFin as we have explained just above will finally be called Intel 7. All this mess comes from the problems, delays and announcements that the blues have made over the years and that finally take shape with this new name already adapted to the next decade.
What are its main improvements? The most important thing is performance, where Intel ensures that we can see an increase per watt that could reach 15% compared to the current 10 nm, although they also affect that it could be 10% in the worst case.
Is it really a lot or a little? Well, being an update of the previous 10 nm and seeing the jump is more than correct, since these percentages are normally those that are achieved in a new node, so calling it Intel 7 is in our opinion more than correct.
They are still FinFET transistors, but there are key optimizations that we did not know before, such as better resistance, better control of power as well as its delivery. We have seen this in Alder Lake processors, where Intel’s efficiency has greatly improved clock per clock.
We return to position ourselves, since if the 10 nm SuperFin are now Intel 7, the old 7 nm are now called Intel 4. What will be the jump here? Considering that it will be the first node in the company to use EUV as an engraving technology, the expectations are really high and for good reason. The blue giant speaks of a 20% gain in performance per watt, which if we take into account that in principle up to 12 layers will be used in each wafer is a very relevant data.
Why? Well, it’s simple. Fewer layers mean greater wafer creation simplicity, lower costs, and higher performance.
Intel will optimize the number of layers to achieve a reduction in power that will be better in terms of performance as we get closer to CPUs that have greater power limitations.
In other words, processors with lower TDP could improve that 20% performance on that node, although we do not know by how much. When will it hit the market and with what architectures? Well, it will be sometime in 2023, it will possibly debut before the middle of the year with Meteor Lake for desktop and by the end of the year it will be the same for Granite Rapids in Data centers and server.
This lithographic process also comes with some controversy because the company has not specified 100% if it is the old 7 nm + node or the one named 7 nm ++ at the time. From the little we know about it, it is more likely that it was the latter because Intel claims there will be another 18% more performance per watt.
In addition, the jump in power reduction is greater and performance is more scalable as the CPU requires less voltage or is limited to it, so again we could see a small more performance gap.
Intel 3 as such will be the end of FinFET transistor technology and technically the forerunner of the biggest leap in company history. For this, this Intel 3 has a higher area density based on the growth of HP, which offers even better resistance, new materials that will improve the interconnections of the layers and with this it will be possible to interconnect more interposers.
The EUV technology here has a lot to say again, to the point that the company has said that the jump will be greater than in the previous standard that we have seen, that is, there is a greater improvement than in the previous nodes. The architecture that will bring this node to life will be Arrow Lake in late 2023 if all goes well or early 2024 at the latest.
It is the biggest change as a concept and novelty that Intel has implemented in its history, because it encompasses a series of far-reaching improvements. The designation A refers to the unit of measurement Angstrom, mainly because the company wants to leave behind the nanometer as such.
It will arrive sometime in 2024, possibly in the first half, although there are already rumors that it could be by the end of the year due to all that we are seeing with the delays in all the companies. Likewise, the main improvement is that we say goodbye to FinFET and we will say hello to RibbonFET, Intel’s implementation of the technology GAA or Gate-All-Around that we already dealt with in its corresponding article exclusively.
The second improvement is the call PowerVia, which is intended for electrical consumption as well as its implementation in the transistor. FinFET was powered by the upper part of the transistor through the same system that routed the signal, which required almost absolute precision and constant innovation in the materials used at each lithographic leap.
Intel 3 is the limit and Intel 20A what it will do with this technology PowerVia It is simple: separate in a new transistor diagram the signal path and the electrical supply, which will now be produced by the lower part of each of them. You do not have to be very smart to see the advantages that before could not be given by the FinFET structure of each transistor: better efficiency, lower consumption, better signal, more stable supply, better control in the Gates, lower signal noise, better internal latencies, not to mention the lowest failure rate per wafer.
How do they do that? Basically a layer is added under the transistors at the back of the wafer where the power cables for each unit are created. Intel is so confident that the results will be good that they could even adapt it to FinFET by spending resources on it.
And they are not even sure they can implement it, but in the words of the blue giant they hope to at least try it. In any case, we are talking about a node that would presumably arrive in 2025, at the end, although it would go into production already in 2024 where regardless of this it is expected to give life to the core architecture Nova lake with Panther Cove and Darkmont as performance and efficiency microarchitectures respectively.