Computer

New Intel CPUs have not been released and are outdated in RAM

The RAMBUS company is one of the veterans in the world of developing new types of RAM, it was famous in the 90s and early 2000s for its RDRAM memories, but they lost the battle against DDR and GDDR. Since then RAMBUS has become the designer of interfaces with RAM memory of all kinds, which it designs internally and then licenses them to third parties as Verilog or VHDL files for easy implementation by CPU designers.

RAMBUS DDR5-5600

Its latest innovation has been the introduction of a DDR5-5600 interface, but not only for common DIMMs, but also for RIMMs used in servers. So future generations of the AMD EPYC and Intel Xeon could implement this memory controller in their perimeter to communicate with the RAM of the system in which they are located. The other half of the interface is placed as a separate chip in the central part of the RAM modules, whether they are DIMMs, RIMMs or any variation of these.

What is the RAMBUS DDR5-5600 controller?

DDR5 RAMBUS oscilloscope

Really, the RAMBUS DDR5-5600 interface has nothing special, it is nothing more than a controller for DDR5 memory or rather, it is the hardware interface that communicates the Northbridge and IMC of the CPU with the RAM memory. It is a piece that, due to its proximity to RAM and to avoid increases in latency and consumption, is placed on the periphery of any processor that uses it.

So far, the DDR5 controllers that have been available are DDR5-4800, but with the arrival of the RAMBUS DDR5-5600, the implementation in CPUs in the short and medium term with support for fifth-generation Dual Data Rate memory becomes possible. Of course, being a recent announcement this will not affect CPUs like the Intel Core 12 that are already in production. On the other hand, other more distant processors that have not yet entered final production could receive these interfaces in their design.

That is, Intel is not going to be able to implement in its new CPUs that this memory interface is about to come out and therefore, its CPUs stay at 4800 MHz like JEDEC, while AMD still has time to achieve it for Zen 4 and thus have a minimum speed of the aforementioned 5600 MHz.

DDR5 Asgard

We cannot forget that a change of this type may involve a series of additional changes in the hardware design that accompanies the CPU, since it also involves variations in the motherboard and its chipset, which are designed around the processor specifications.

Keep in mind that there is already higher speed DDR5 memory, but the particularity of this RAMBUS DDR5-5600 controller is none other than allowing a relationship between the CPU and this type of RAM without having to lower the clock speed of the memory controller on the processor side and increase latency because of it. In other words, post-Intel Core 12 CPUs that use this RAMBUS DDR5-5600 interface with memory of the same type will not need to put the CPU in Gear 2 mode to use this type of memory, other than not requiring XMP.

Designed for server RIMMs

DDR5-5600 diagram

However, the RAMBUS DDR5-5600 controller is designed for use in RIMM modules and therefore we will see its implementation in Intel Xeon Sapphire Rapids. RIMM modules make use of a buffer that is placed between the DRAM itself and the controller and is responsible for distributing the signals that include the addressing and command information in order to have a better integration of the signal. The counterpart of this is that it increases latencies and as a consequence it is required that the flash controller inside the RIMM module is designed for specific speeds, as is the case at hand.

Related Articles