No chip made on TSMC’s N3 or 3nm node has yet appeared on the market, however, the latest news is really bad as an item that has been improving over time and technology after technology would have stagnated for good. . Has SRAM finally stagnated?
The often misunderstood Moore’s Law has seen several announcements of its end in recent years. However, with TSMC’s latest announcement regarding its 3nm node, that claim could become true. At least in the face of a type of transistor combination widely used in all types of processors and this will be a brake on chip development in the following years.
Bad news: they can no longer cut the size of the SRAM
As usual with each new manufacturing node we find that the transistors, whether they are logic or memory, scale to a smaller size. In the case of memory, this means larger internal memories or simply being able to fit more of them in the same space. However, TSMC’s 3nm node brings some very bad news when it comes to scaling the size of SRAM from the 5nm node currently in use.
Well, during a conference at the 68th edition of the IEEE International Electron Devices Meeting (IEDM) where more than 1000 engineers from the industry have gathered, and, therefore, the people who design the hardware you use in your PCs, the short and medium term developments of the industry are discussed. The folks at TSMC have talked about their 3nm node that will be used by future Ryzen processors and also by Apple, as well as future generation GeForce and Radeon graphics cards. What has happened? The Taiwanese foundry has released very bad news.
To understand what is happening we have to start from the fact that TSMC has two variants of its 3nm node.
- The first called N3B can make SRAM with a density of 0.0199 square micrometers per bit, a reduction of only 5% from the 5nm node,
- As for the other variant, N3E, there is no scaling of any kind. Which means that the area occupied by the SRAM inside the processor will increase.
It is an essential piece
Due to the fact that SRAM is used to build internal memories that are essential for processors to work, such as registers and caches. Therefore, it is an essential element and this limitation could not jeopardize many of the advances that are expected for future generations of processors, where the tendency is to bring the memory closer to the processor in order to reduce the latency problem. and energy consumption when moving the data.
Thus, to the problem of data movement and the energy cost we must add that of storage. Not facing RAM memories since they use DRAM memory, but inside the processor. In other words, the size of the caches will not increase and the addition of new cores will be less than expected compared to the progress we have had in recent years, precisely because of this limitation when it comes to scaling SRAM memory from one node to another.
Is it a unique TSMC problem?
Since Intel recently made the decision to become a chip maker not only for their products, but also for third parties, they have entered into a fierce competition with the Taiwanese foundry for others to make their chips. At the moment we do not know the density of the SRAM in the Intel 4 node, which will be the one that will coincide in time with regard to the pieces that will go on the market. Although everything indicates that the process of the American manufacturer is a little below SRAM in terms of density.
In any case, all this indicates that the development of 3DIC memory configurations made up of several stacked chips and that was adopted by AMD with the Ryzen X3D and the V-Cache will be a more common solution in the future than we expected and not a simple experiment, since it will be the only way to implement a last level cache with enough capacity so that the SRAM scaling limitation does not result in a bottleneck. The other remedy is to build bigger chips, but with rising costs it’s abundantly clear that hardware, if expensive now, is in danger of becoming a luxury item.
