The giant Samsung Electronics, one of the most important international companies in the world of semiconductors, has presented the pfirst 128 GB DRAM memory solution that is compatible with CXL 2.0, stands for Compute Express Link, an interconnect standard that allows the CPU to communicate with different types of memory at very high speed. This standard is based on the PCIe interface both physically and electrically.
To complete the development of this new high-performance memory module, Samsung has relied on with the collaboration of Intel, which means that said development was carried out on a platform based on an Intel Xeon CPU. The South Korean company already marked an important achievement in the past when it developed the first DRAM based on CXL 1.1, back in May 202, so this new device based on CXL 2.0 is another example of the good work that Samsung is doing.
According to Samsung, this new memory supports the PCIe Gen 5 x8 interface (eight lanes), and is capable of working with a bandwidth of up to 35 GB/s. Jangseok Choi, Vice President of Samsung Electronics New Business Planning Team, commented:
“As a member of the CXL Consortium Board of Directors, Samsung Electronics continues to be at the forefront of CXL technology. This innovative development highlights our dedication to further expand the CXL ecosystem through strategic partnerships with industry leaders in data centers, servers, and chipsets.”
Jim Pappas, director of technology initiatives at Intel Corporation, expressed his delight in working with Samsung to foster a thriving CXL ecosystem, saying:
“Intel is delighted to be working with Samsung as they invest in a vibrant CXL ecosystem. Intel will continue to collaborate with Samsung to promote growth and adoption of CXL products innovators across the industry.
It is important to note that one of the key features of the CXL 2.0 standard is its support for memory pooling, a memory management technique that consolidates multiple blocks of CXL memory on a server platform to create a specific pool, allowing hosts to dynamically allocate memory from that pool on an as-needed basis.
Everything that I have just commented translates into a increased efficiency and reduced operating costs, all without having to give up a high level of performance. This memory can be combined with the main DRAM, and is of great interest in such important sectors as artificial intelligence and deep learning. Samsung hopes to start mass-producing it later this year.
