It is true that we enter fully into the field of speculation and perhaps also within the personal opinion of a server, but seeing the latest advances in the sector it does not hurt to look ahead and understand the moment in which we are and where we are headed. The scenario is simple: stagnation of the sector and almost no improvements regarding the future of the water blocks. What is the next step?
Goodbye to platform compatibility between Intel and AMD
Currently and seen with Zen 3 and Alder Lake we are in a phase where the game has changed and will change even more. The problem is the efficiency of the blocks due to the arrangement of the processor dies. AMD currently has three dies between CCD and IOD, Intel is going to keep only one, where it is also focused on the PCB.
What does this mean? Well, for a short time the blocks have been designed to improve the temperature based on the arrangement of the dies, which leaves compatibility as such in the lurch. It is not the fact of incompatibility, but the fact that a coldplate and inserts for AMD will not achieve the performance of the competition if we export these to an Intel processor, and vice versa.
In this sector you compete for deltas of tenths, so the blocks are being designed based on the platforms and with all this in mind. Why? We have the perfect example at Intel and AMD today.
In the case of Intel, having the impact of the water under pressure through the jet in the center of the coldplate is the most optimal as long as the fins are oriented transversely to the die. In the case of AMD, the same system is currently inefficient, even if the block is turned in Goofy mode, and the impact of the water should be made in the part of the two CCDs and not in the center, because the dispersion of the water implies cooling. to the IOD at the same level as the CCDs, when the former only consumes a maximum of 20 watts, while the rest is from the latter.
The future of CPU water blocks, how to optimize flow?
Displacing the water inlet so that the impact and dispersion are greater where the CCDs are located is not a design problem, it is a flow problem. Varying the water outlet according to the new inlet means very high pressure zones in the second and practically none in the first.
Therefore, this represents a paradigm shift in future blocks, since the number of CCDs on desktop will not increase since the PCB area would have to be fired in the Threadripper style, much better managed in this regard without a doubt.
Therefore, as long as AMD continues with chiplets of a considerable area and does not increase that of the PCB, the problem will remain the same and manufacturers do not know how to solve this.
The only thing they can do is improve the coldplate and the fins, occupying more and more useful area trying not to lose too much flow to maximize the performance of the system.
EK with its Quantum Magnitude has achieved something similar, with a solid insert that restricts the passage of water in two different sections before introducing it to the jet, to later maximize the flow in a coldplate with a greater dissipation area of 43.1 x 35 , 3 mm with channels only 260 µm thick. And there is currently the limit, because the blocks with peltier cells or TEC are not for everyone due to the high consumption and the possible assembly errors that would leave the PC like a nice desktop paperweight.