The idea of stacking several chips and interconnecting them vertically 3DIC, in the market we have already seen it in the form of HBM memory, but the fact of unifying memory and logic in a 3DIC design or even several layers of chips based on logic is a lot more difficult. While in the case of HBM memory we have seen designs of up to 4 stacked chips, in the case of logic + memory or logic + logic we have seen only two-chip compositions.
Stack up to 4 layers of chips in a 3DIC design
Although with the HBM memory found in high-performance graphics cards it already uses a 4-layer configuration, all memory, The American Institute of Microelectronics, the IMC, has achieved a technological milestone that allows up to 4 layers of chips or semiconductors to be stacked forming a single chip in a four-layer 3DIC configuration.
The approach proposed by the IME is based on combining a pair of wafers face to face, in such a way that both are connected on the same side, which we are going to call A. To then connect the other two chips at the ends but connected the reverse face or B. Once this procedure has been done, channels are created for the pathways through silicon to pass through the four chips, thus allowing interconnection between the four chips that make up the 3DIC composition.
The problem with a stack of chips is thermal choking between the different chips, which becomes more complex as the stack gets larger in terms of number of components. It is for this reason that for example the HBM 3 memory has not yet seen the light due to the internal debate on whether to increase the number of chips at a lower speed and with it the width of the bus or the speed of the bus itself. In both approaches the challenge is the same, the temperature.
Will it be adopted by Intel and / or AMD?
Well, we do not know, at the moment the bet of Intel and AMD seems to be for 2.5DIC systems in which several chips are connected in a common interposer, some of them are classic chips and the others are 3DIC. At the moment both AMD and Intel do not plan to use pathways through silicon, but what is called Silicon Bridges or Silicon Bridges, at least to connect the different components of the MCM on the interposer.
Another different thing is the vertical composition, the fact of adding up to 4 chips allows a less interesting concept. Which would consist that like the Lakefield separating the Chipset or Southbridge from the rest of the CPU on the one hand, on the other it would be based on the addition of additional last level cache in one or the two remaining layers. Top-notch cache augmentation with 3DIC is critical for performance in certain applications that require both bandwidth and memory capacity. Where the solution is usually to use complex HBM memory systems how future Intel Sapphire Rapids will carry.