If there is a concept that you are going to hear more and more when talking about new processors, this is RISC-V, and that is that more and more designs are appearing based on this totally free and open set of registers and instructions. The last? A processor called Esperanto, which is made up of neither more nor less than 1000 cores with ISA RISC-V and optimized for artificial intelligence.
One of the things that differentiates the RISC-V concept from the rest is that it is not a complete processor whose design has been licensed to third parties, as is the case with ARMs, but rather a fully scalable ISA that allows the creation of totally different and focused processors. to specific applications. This has made it the basis for designing a series of new domain-specific processors. Which base their design on cuts and additions focused on a specific niche.
One of these markets is that of artificial intelligence, where units that are not usually found in CPUs are necessary. As is the case with tensor-type units or also known as systolic arrays. While other functions that are not necessary are cut out completely or limited. This is something that is thanks to the modularity of RISC-V and the fact that anyone can make a processor from scratch with just enough knowledge. The last processor that has caught our attention is a 1000 core RISC-V chip of an emerging company called Esperanto Technologies and that among others has come to draw the attention of Samsung.
This is the ET-Soc-1, the processor with more than 1000 RISC-V cores for AI
The name of the processor we are talking about is ET-SoC-1 and is based on no less than 1092 cores, four of which are high-performance RISC-V cores and are called ET-Maxion. His work? Run the operating system, in this case Linux, and take care of the general purpose code. So they are the conductors of the entire orchestra of the entire chip.
As for the 1088 cores remaining inside the chip, these are also RISC-V and are called ET-Minion. Although they are of a different nature since they are optimized for the use of deep learning algorithms, where the use of tensor units is key. Let’s not forget that a very common type of operation are the so-called operations between matrices. Without the corresponding optimizations, a processor can become between ten and a hundred times slower when executing them.
The 1000+ RISC-V cores are so simple that do not use out-of-order execution and also the whole chip lacks a complex caching system. Due to the fact that these are usually counterproductive when executing this type of algorithm. Instead, the processor has 152 MB of SRAM memory within it. Apart from interfaces with external RAM memory, of the type LPDDR4X on a 256-bit interface. Regarding storage and peripherals, it has support for eMMC flash memory and has a 8 lane PCIe Gen 4 interface. Apart from others with more limited bandwidth.
