What both AMD and TSMC are doing is very impressive, perhaps not at the level of Intel with Foveros (for now) but what is certain is that although technologically they are not up to the task for now, in performance they are going to position themselves as leaders. (except surprise with Alder Lake-S).
AMD Zen 3 3D Cache, a performance jump of 15% in gaming
The numbers slipped by Lisa Su give that figure as an average result, but now we know the curiosities of the whys. And it is that adding one more vertical chip as an increased cache will not be, as was being speculated, a level 4 cache, or in other words, it will not be the typical Victim Caché technically speaking.
Everything is much simpler from theory, but from practice the numbers are overwhelming and we explain ourselves.
What AMD achieves with this vertical cache is that Windows and CCDs see the added chip as “transparent”, that is, there is no physical change to the software or hardware in their mode of operation between cores and the IOD.
What you will see is one more L3 cache block, which will be manufactured at 7nm by TSMC and will measure a whopping 6 x 6mm (36mm2) connected directly to the CCD caches via TSV. And here comes the magic, because in the case of the 5950X that was shown at the time with this technology we speak of no less than 192 MB of L3 in total for the 64 existing of the original model that we can currently buy.
TSV figures dizzying, at the height of Intel
Each CPU will have more than 2 TB / s of bandwidth thanks to this new cache and its TSV connections, which we now know are made by Bumps in what is called as “Face Down”, Each TSV is connected from the FEOL of each CCD to the Bonding Surface through Nails coppermade. They are in direct contact with the BEOL of this new cache, which allows the exchange of information from substrates and caches.
To give us an idea of the complexity of all this vertical stacking, it is calculated that for every 4 MB L3 partition that has a CCD there is 3000 TSV with a size that includes them between 6.1 μm and 17.3 μm thick.
To square the circle, more stratospheric data are given, since in the SMU they are calculated 56 TSV and 14 more in the so-called test area.
What do we have in total in the new 5950X? Well, a whopping 24070 TSVs to connect both substrates, where as we have said before the area of the new AMD 3D Cache is only 36 mm2. Undoubtedly staggering numbers and that will allow AMD to beat Intel to the ground, at least momentarily.
