During these days the Hot Chips is being held, a symposium where several of the manufacturers and designers of the hardware sector present their latest technological advances. The difference between Hot Chips compared to other events is that it is not a commercial conference and therefore we are not at a fair, but rather an event aimed at engineers and hardware enthusiasts where the latest technological advances are explained, which it is their motivation and how they work. As is the case of the V-Cache of which AMD has given new details.
AMD gives new details of its V-Cache for the Zen 3
A few months ago, AMD surprised us all with something we weren’t expecting. The addition of an SRAM memory chip on top of the Zen 3’s CCD Chiplet, which we learned about was already designed for it from the ground up. The idea is none other than to expand the capacity of the L3 cache that is shared by all the Zen 3 cores within the CCD chiplet and with it the performance. The reason for the performance increase is very simple, with this the amount of data that is in cache increases. What makes the accesses to the RAM to access the data are reduced as there is more data in the last level cache and with it increases the performance up to 15% without changing the rest of the chip.
What is the new information AMD has given us about its V-Cache? Well, the way in which they have achieved it, and that is that they have used several microbumps to communicate the SRAM module with the CCDwhile the wiring is the classic via silicon or TSV. The vertical interconnection of the CCD Chiplet with the additional SRAM has been made with dialectric-dialectric interconnection with direct copper-to-copper bonding. This type of interconnection has been developed in conjunction with TSMC.
The microbumps used for interconnection are of 9 micrometers in size, 10% smaller than the ones Intel used at Foveros for Lakefield. It must be taken into account that the key for vertical 3D interconnections is the number of interconnections, since the strategy to increase the bandwidth between the two parties is not to increase the clock speed of each interconnection, but the amount of the same in order to keep the consumption for data transmission as low as possible.
The V-Cache is only the beginning, AMD tells us
It is no secret that the future lies in the 3DIC integration of chips, both logic and memory. The demonstration of this is that we are seeing non-monolithic configurations that are of the 3DIC or 2.5DIC type in the different designs under development of the different manufacturers.
At the moment we only have cases of stacked memories like V-NAND or HBM in their different flavors and soon we will have logic and memory. But in the near future it is possible that we will see from AMD configurations where IOD and Chiplets are one on top of the other. Which does not take us by surprise, it is something that was seen coming, the difference is that now AMD has just confirmed that it is working on it.
So it is more than possible that future CPUs such as those based on AMD Zen 4, not only may they use V-Caché but we may see them in a 3DIC configuration or of another type different not only from the classic monolithic processors. one-piece, but also different from the 2.5DIC chiplet configuration that we have seen in the AMD Ryzen 3000 and Ryzen 5000.