TSMC will reduce the cost of its 3 nm by reducing the EUV layers

We are still waiting for the 5nm node to be standardized on PC, which we expect by 2022. TSMC cannot sit idly by and must have its 3nm node ready. Which will begin to mass-manufacture chips from the second half of 2022. Of which we already know that the first customers will be both Apple and surprisingly also Intel. As each node will start creating smaller and low-consumption chips before making the leap to the more complex ones such as CPUs and GPUs for PCs, for which we will have to wait until 2023 or even 2024.

TSMC’s idea for 3nm, reduce the number of EUV layers

The deployment costs of each manufacturing node are increasingly high, the space race that is the world of semiconductors has made more and more manufacturers have been erased from continuing in it. Currently we can count the number of foundries that can with the most advanced nodes using the fingers of one hand and we would have some of them left over.

High costs have meant that TSMC has to spend a whopping $ 100 billion to deploy the new nodes in the next three years. An immense capital of which the different investors fear that it will have a much lower return than in previous generations. The biggest expense on the new nodes? The EUV machines whose high cost will make it the most expensive node to date, which is why TSMC has decided to implement a continuous improvement plan, which allows it to cut the EUV equipment for its 3 nm node.

How do you plan to achieve it? Well, it seems that by cutting the number of EUV layers that would be used at the 3 nm node. Which are increasing with each new TSMC manufacturing node. These started to be 4 in node N7 + of TSMC, to increase to 5 in node N6. For chips at 5 nm, between 14 and 15 EUV layers will be necessary and the thing goes to 25 layers with 3 nm. TSMC’s plan? Reduce them to 20 to lower costs.

A war to choose the best clients

Intel TSMC

The entry of Intel as a competition for TSMC together with the support of the US government, which wants to convince that the manufacturing takes place not only on US soil. but by one of the large companies in that country. This situation is the reason why TSMC has had to opt for certain solutions to reduce costs.

To this day, the TSMC N3 or 3nm node is one of the most advanced in the absence of Intel presenting its own. So what is the problem? Well, due to the fact that an increase in the deployment costs of each node increases the cost of the wafers and reaches the point where using a more advanced node is not economically viable.

Not all hardware components require extremely advanced nodes to function, this reduces the usefulness of the more advanced nodes and makes the hardware that uses them more expensive. Hence, companies like TSMC are looking for ways to lower the costs of their future nodes. More when now it seems that it will have a much fiercer competition, after years in which everything pointed to an absolute monopoly due to the immobility of its competitors.

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