If by now you had not heard of UCIe, the acronym for Universal Chiplet Interconnect Express don’t worry, because in the short and, above all, in the medium and long term, it will become a term that will become extremely common when talking about processors, APUs, and SoCs. And it is that if until now it already seemed clear that the future was chiplet, with the birth of this standard the doubts are cleared and, in addition, the door is opened to a higher level of collaboration between manufacturers.
As you know, for some time now more and more manufacturers are leaving behind chip designs in which all the computing capacity is supported by a single particularly complex element, to adopt designs in which the workload is distributed among multiple elements. To understand it quickly, we can say that the architecture inside the package is more complex, but that it is made up of simpler elements.
This has multiple advantages, ranging from the modularity of the integrated ones, to the reduction of costs in the face of defective units that leave the production lines. This is the reason why we have been seeing this model in the SoCs of our smartphones and tablets for so long, and why both AMD and Intel have also brought this integrated model to the x86 architecture, making it no longer an almost exclusive heritage. from ARM.
Until now, however, no clear standard had been defined regarding the chips that are integrated into these packages, so the interconnection between them corresponds to the architecture defined by each manufacturer. UCIe intends to change that, with a universal standard for interconnection between the components of a chiplet. In other words, when designing a package, the manufacturer can integrate chips from different manufacturers.
The success of a standard depends, of course, on whether or not the industry decides to adhere to it, but it seems that UCIe will have no problems with this problem, since the consortium that has initiated its definition is made up of, in alphabetical order, AMD, ARM, ASE (Advanced Semiconductor Engineering, Inc), Google, Intel, Meta, Microsoft, Qualcomm, Samsung and TSMCthat is to say, practically all the main technologies related to the design and manufacture of chips are behind UCIe and, therefore, we understand that they will opt for this new standard when designing new integrated chips.
And what does UCIe offer? The key is what I mentioned earlier, that with a common specification to define the interconnection of integrated chips, the design possibilities of processors, APUs and SoCs are exponentially expanded. without the manufacturers of their components having to adjust to the particularities of the design of each chiplet. Can you imagine an APU in which the performance cores are from Intel, while the efficiency cores have been signed by, say, TSMC, and the graphics section falls on an AMD chip? Well, with the standardization proposed by UCIe, this is possible, at least on the hypothetical level.
Of course, since UCIe has been defined by the sector itself, it includes aspects such as 2.5D and 3D architectures, with which AMD has been experimenting for some time and that we will soon see in other manufacturers. And in terms of performance, this first specification, which is not yet final, proposes an interconnection bus with a speed greater than a terabyte per second, with a very low level of consumption, of only 0.25 picojoules (a joule for 10-12) per transmitted bitso efficiency is also a very notable factor.
As I said before, the first UCIe specification, which is based on PCI Express with Compute Express Link, not final yetbut in any case it does point to a future in which the integrated ones on which the computing capacity of our devices will depend, from smartphones to PCs, but also connected vehicles and many other devices of all kinds, will be based on this new standard that has seen the light today, and that marks the destiny of the integrated of the future.
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