It is an open secret, AMD is preparing the launch of a hybrid architecture based on Zen 4 that will start from a similar approach to the one we saw in Alder Lake-S, and later in Raptor Lake-S. This means that said architecture will adopt a configuration of high-performance cores and high-efficiency coresboth capable of working simultaneously and designed to cope with different tasks optimally.
However, while this Zen 4-based AMD hybrid architecture builds on that same foundation, the execution is different, and it’s important to keep this in mind because, in the end, it will make both designs position in a different way despite having that same starting point.
As our regular readers may already know, both Alder Lake and Raptor Lake use a high performance core block based on the Golden Cove and Raptor Cove architecture, respectively, and a block of high-efficiency cores based on the Gracemont architecture.
Each of those core blocks has important differences at all levels: core size at the silicon level, working frequencies, cache subsystem and total number, specialized hardware and much more. Therefore, the performance difference when running tasks on one or another block of cores can be huge. Intel uses two totally different architectures.
AMD will use Zen 4 in its new hybrid architecture
Unlike the chip giant, which, as we have already said, uses two completely different architectures, AMD is going to use Zen 4 on both high-performance cores and high-efficiency cores. This might sound like bad news, but nothing could be further from the truth. Zen 4 is a highly scalable architecture, and using a trimmed version to create high-efficiency kernels is an entirely wise decision.
I know you may be wondering how AMD is going to scale the Zen 4 architecture in that new hybrid design, and the answer is very simple, reducing the amount of cache and lowering the work frequencies. These are two simple changes, but very important both in terms of performance and consumption, and also in terms of space occupied at the silicon level.
Consider that the space occupied by the L3 cache is so large that, to shape the Ryzen 7000X3D, AMD has had to stack the extra 64 MB of cache on top of a chiplet, which means that said cache occupies the same space as a chiplet with 8 cores and 32 MB of L3 cache. In the case of the efficient Zen 4 cores used in that hybrid architecture we could find a configuration of between 8 MB and 16 MB of L3 cache, depending on the total number of activated cores.
Shrink L3 cache it would affect the space occupied at the silicon level, which would be much less, but also the performance, especially in applications that depend on this type of memory, such as games. On the other hand, AMD could also reduce the working frequencies, which would go from a maximum of 5 GHz in high-performance cores to a 4 GHz maximum on high-efficiency cores.
It goes without saying that the lowering of the L3 cache and that 1 GHz reduction would, together, make a highly efficient Zen 4 core offer a performance similar to that of a Zen 2 core. Taking into account how well processors based on this architecture still perform, it is clear that this data is positive, and that these high-efficiency cores they could compete without any problem with their Intel equivalentssince these are more or less at the level of Skylake in terms of IPC.
Core distribution: everything points to a monolithic design
At first it seems that AMD will use this hybrid architecture based on Zen 4 only in APUs, that is, in solutions that integrate CPU and GPU in the same package, and that the two types of cores will be present in the same silicon chip, that is , a split into multiple chiplets will not occur.
This leads us to talk about a design of monolithic Core, and the first data we have points to two possible configurations, one that would have four high-performance cores and four high-efficiency cores, and another that would have two high-performance cores and four high-efficiency cores.
The first configuration should have 8MB L3 cache on its high-performance cores and 4 MB of L3 cache on its high-efficiency cores. The second configuration would keep the 4MB L3 cache on its high-efficiency cores, and reduce the L3 cache on the high-performance cores to 4MB, since it would only have two of these cores. In total, a 4 + 4 configuration would have 12MB L3 cacheand a configuration of 2 + 4 would have 8MB L3 cache.
Keep in mind that these data are estimates, and that we do not yet have confirmed the exact amounts, which means that these figures could vary. However, considering that a Ryzen 7 7840HS APU, based on Zen 4 and equipped with 8 high-performance cores, adds 16 MB of L3 cache I believe that the values that I have given you they make a lot of sense.
In a performance test filtered under Cinebench R23 we have been able to see that the high-performance cores reach 5 GHz, but on average they move between 4.2 and 4.3 GHz stable. The high-efficiency cores reach 4 GHz, but their average remains a bit below 3GHz. With regard to consumption, the values we have seen point to between 7 and 8 watts in high performance dual cores and 5 watts in high efficiency quad cores. This leaves us with a total consumption of 13 watts.
Final Notes: Hybrid Designs Have Great Potential
AND They have been proving it for years in the mobile sector, where different architectures coexist and combine to create chips with up to three different core blocks. Intel realized this reality and decided to bet on it with Alder Lake-S, and the results were so good that it repeated with Raptor Lake-S. The next to jump on the bandwagon will be AMD, although it seems that for now it will do so in a limited way and focused on its APUs.
That new hybrid architecture based on Zen 4 will keep the DDR5 memory supportcould be manufactured in the node TSMC 4nm, which would make it even more efficient, and it will be accompanied by a GPU based on the RDNA3 architecture. Its release could take place between the end of this year and the beginning of next year, and according to some rumors it could end up becoming the brain of Steam Deck 2.
We don’t know if AMD will eventually market versions of these APUs for the PC sector, or if they will be limited to laptops and mobile devices, but with the information we have right now I would lean more in favor of the second option. However, I believe that even if this limited adoption occurs in both sectors, we would be facing a first step that would serve as a spearhead for extend, in coming years, that hybrid design to other levels.
