So far the CPUs or the part in charge of them in the Intel and AMD APUs generally use homogeneous configurations, which means that all the cores are symmetrical. But we know that both Intel and AMD will bet on heterogeneous configurations, based on an asymmetric configuration of cores. This means important changes also in the infrastructure
Hybrid cores in future CPU architectures
We know that both AMD and Intel are going to implement hybrid configurations on your CPUs, which translates into a system similar to the ARM DynamiQ, but in CPUs with ISA x86. The idea is none other than to accompany conventional cores with other simpler cores and therefore of smaller size and consumption. Its utility? Today, PCs have a huge amount of active background tasks that drain resources and power from the larger cores and that will benefit from the addition of the lighter cores.
Due to the small size of these cores, implementing them in large numbers is much easier than increasing conventional cores within future processors. For example, according to rumors we know that from Alder Lake-S to Raptor Lake-S Intel will not increase the number of cores with the name ending in Cove that are the most powerful, but Gracemont cores that are the light cores. In the case of AMD we will have to wait longer and
Increasing the number of cores or other types of components means an increase in the number of communication channels, which in the architecture of an SoC assume that the central part of the same increase to considerable levels. To the extent that in many designs it has been necessary to divide an entire CPU into several different components. Both asymmetrically, in the case of AMD since Zen 2, and symmetrically, which Intel will launch with Sapphire Rapids first on servers and Meteor Lake later.
How do multiple cores communicate with each other?
Today all the processors on the market can be considered an SoC, if we are demanding from the point of view of architecture. The reason is that we have the different components of the SOC communicated with each other through the central component which is the Northbridge. Which is growing in complexity the more components it has to communicate with each other and the more data it has to transmit between them.
The Northbridge integrated in most SoCs, apart from incorporating a series of fixed function mechanisms related to the communication protocols with the RAM memory and peripherals, They use a mesh interface for communication between the different elements.
How does this interface work? Well, very simple, we have a certain amount of components connected to each other through the mesh interface in the Northbridge. So if we have N elements, then there will be N ^ 2 interfaces. With which it is logically concluded that as the number of components increases as well as the bandwidth necessary for them, the size of the Northbridge also increases as the size of the Crossbar increases.
CPUs with hybrid cores will mean a considerable increase in the number of cores. Which will result in an increase in the number of interconnections. Although for this we already have the solution in the form of the implementation of intelligent network controllers in the Northbridge. Which will evolve longtime SoCs into NoCs in order to more efficiently support not only the growing number of cores, but also to more efficiently manage internal communication within the processor.
